Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process

We propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF (ACFF) with low dynamic power and short delay overheads in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. We designed four FFs composed of the master latch with PMOS pass-transistors to reduce delay time overheads and the slave latch with stacked transistors for high soft-error tolerance. We evaluated radiation hardness of those FFs by TCAD simulations and α irradiation test. The α irradiation results show that error probabilities of the proposed FFs are 1/400 1/130 smaller than the conventional radiation-hardened stacked FF. The experimental results show that PMOS pass-transistors can effectively suppress soft errors in the terrestrial region with a low-delay overhead.